The disclosed embodiments of the present invention relate to mitigating frequency deviation effects caused by a variable-rate clock, and more particularly, to a polar transmitter having a digital processing block used for adjusting a frequency modulating signal for frequency deviation of a frequency modulated clock and a related method thereof.
A digital polar transmitter offers some advantages, such as a potential for reducing complexity and current consumption in the modulator path as well as eliminating the problem of image rejection, thus the polar transmitter is more suitable for implementation in advanced complementary metal oxide semiconductor (CMOS) processing technologies. More specifically, the digital polar transmitter is a transmitting device that splits a complex baseband signal explicitly represented by an amplitude-modulated (AM) contented component and a phase-modulated (PM) contented component, instead of an in-phase component and a quadrature component. These two components are then recombined into a radio-frequency (RF) output to be transmitted over the air. For example, an all-digital phase locked loop (ADPLL) may be disposed in a frequency modulating path to generate a frequency modulated clock, such as a clock output of a digitally-controlled oscillator (DCO), in response to the PM contented component, and the frequency/phase modulated clock is processed by a following stage such as a digitally-controlled power amplifier (DPA).
In the digital polar transmitter, almost all variable-rate and fixed-rate clocks (except for the frequency reference, FREF, clock, of course) are generally obtained by edge-division of the frequency modulated clock (e.g., a DCO clock). More specifically, to save area and power, there is no dedicated fixed-rate PLL used for the generation of high-frequency clocks. Since the DCO undergoes FM data modulation, all the derived integer-divided clocks will experience time-variant instantaneous frequency perturbations. In other words, any clock derived from performing frequency division upon the DCO clock would have a time-variant clock frequency due to the FM data modulation. The transmitter (TX) circuits normally assume time-invariant clock frequencies, therefore certain operations may be affected when the clocks actually have time-variant clock frequencies. One solution may run a clock divider at a high clock rate to compensate the frequency deviation effect and create a clean clock. However, this is power and area consuming, and is not applicable for resource-limited applications.
Thus, there is a need for an innovative design, which is capable of effectively compensating the frequency deviation effect by using simple digital signal processing means.